1. Field of the Invention
The present invention relates to a sample hold circuit for use in a time-interleaved A/D converter, and in particular, to a sample hold circuit for use in a time-interleaved A/D converter including a plurality of low-speed pipeline A/D converters which are parallelized, and a time-interleaved A/D converter apparatus utilizing the same sample hold circuit.
2. Description of the Related Art
A time-interleaved A/D converter including a plurality of low-speed pipeline A/D converters which are parallelized is an architecture capable of achieving high-speed sampling.
FIG. 1 is a block diagram showing a configuration of a prior art time-interleaved A/D converter, and FIG. 2 is a timing chart showing an operation of the A/D converter of FIG. 1. FIG. 3 is a timing chart showing an operation of the A/D converter of FIG. 1 when a clock skew occurs.
Referring to FIG. 1, an analog input signal Vin is inputted to a plurality M of sample hold circuits 1-1 to 1-M, and thereafter, sample and hold processing is executed based on clock signals CK1 to CKM having mutually different timings shown in FIG. 2. The output signals from the sample hold circuits 1-1 to 1-M are A/D converted by corresponding A/D converters 2-1 to 2-M, respectively, and then, A/D converted signals are outputted to a switch 3. Then, the switch 3 is sequentially switched over so as to select the output signals in an order of the A/D converters 2-1, 2-2, . . . , 2-M based on a clock signal CK that is a logical sum signal of the clock signals CK1 to CKM, and a digital output signal Vout of the result of A/D conversion is outputted from the switch 3.
That is, in the case of the structure of the M channel of FIG. 1, the sample hold circuits 1-1 to 1-M of the channels perform sampling every interval Ts in accordance with the clock signals CK1, CK2, . . . , CKM, respectively. Each of the sample hold circuits 1-1 to 1-M samples the analog input signal Vin when the corresponding clock signal has a high level and enters the hold phase in which the signal sampled at a low level is held. In this case, when the A/D converters 2-1 to 2-M of the M channel are used, assuming that the sampling time in one channel is Ts, then the hold time becomes (M−1)Ts. As compared with the A/D converter of only one channel that samples the analog input signal Vin in a time interval Ts/2 and holds the same in the remaining time interval Ts/2, the architecture of the time-interleaved A/D converter has such features that an increase in speed can be achieved with lower power consumption because the conversion rate per channel can be remarkably eased by prolonging the sample and hold time by M times without changing the overall conversion rate.
The prior art documents related to the present invention are as follows:
Patent Document 1: Japanese patent laid-open publication No. JP 2003-158432 A;
Patent Document 2: Japanese patent laid-open publication No. JP 2003-158434 A;
Patent Document 3: Japanese patent laid-open publication No. JP 2004-139268 A;
Patent Document 4: Specification of U.S. Pat. No. 7,227,479;
Non-Patent Document 1: Ken Poulton et al., “A 1-GHz 6-bit ADC System”, IEEE Journal of Solid-State Circuits, Vol. sc-22, No. 6, pp. 962-970, December 1987;
Non-Patent Document 2: M. Gustavsson et al., “A Global Passive Sampling Technique for High-Speed Switched-capacitor Time-interleaved ADCs”, IEEE Transactions on Circuits and Systems-II: Analog and Digital Signal Processing, Vol. 47, No. 9, pp. 821-831, September 2000;
Non-Patent Document 3: Huawen Jin et al., “A Digital-Background Calibration Technique for Minimizing Time-Error Effects in Time-Interleaved ADC's”, IEEE Transactions on circuits and systems-II: Analog and Digital Signal Processing, Vol. 47, No. 7, pp. 603-613, July 2000;
Non-Patent Document 4: Jonas Elbornsson et al., “Blind Adaptive Equalization of Mismatch errors in a time-interleaved A/D Converter System”, IEEE Transactions on circuits and systems-I: Regular papers, Vol. 51, No. 1, pp. 151-158, January 2004;
Non-Patent Document 5: Steven Huang et al., “Blind Calibration of Timing Offsets for Four-Channel Time-interleaved ADCs”, IEEE Transactions on circuits and systems-I: Regular papers, Vol. 54, No. 4, pp. 863-876, April 2007;
Non-Patent Document 6: Zheng Liu et al., “Simultaneous Compensation of RC Mismatch and Clock Skew in Time-Interleaved S/H Circuits”, IEICE Transactions on Electronics, Vol. E89-C, No. 6, pp. 1-8, June 2006;
Non-Patent Document 7: Zheng Liu et al., “Timing Error Calibration in Time-interleaved ADC by Sampling Clock Phase Adjustment”, Proceedings of IEEE Instrumentation and Measurement Technology Conference (IMTEC 2007), May 2007.
However, since the sampling is performed practically in positions different from the ideal ones as indicated in FIG. 3 due to mismatch between channels, the clock skew occurs and becomes a factor to significantly deteriorate the performance of the time-interleaved A/D converter. When the clock skew conforms to the Gaussian distribution that has a standard deviation δskew, the signal to noise and distortion power ratio (hereinafter referred to as an SNDR (Signal to Noise and Distortion Ratio)) of a time-interleaved A/D converter of M channels and a resolution of N bits are expressed by the following equation:
      SNDR    =                  -        10            ⁢                          ⁢              log        ⁡                  (                                                                      M                  -                  1                                M                            ·                              1                                                      (                                          2                      ⁢                      π                      ⁢                                                                                          ⁢                                              f                        in                                            ⁢                                              σ                        skew                                                              )                                    2                                                      +                                          2                3                            ⁢                              1                                  2                                      2                    ⁢                                                                                  ⁢                    N                                                                                )                      ,
where fin denotes a frequency of the input signal Vin. FIG. 4 is a graph showing an SNDR [dB] with respect to a timing error [pico-second] in the A/D converter of FIG. 1. That is, FIG. 4 shows such a case that the influences of skew to the SNDRs of resolutions of 10 bits, 12 bits and 14 bits are plotted when the number M of channels is infinite and the input frequency fin is 10 MHz and 50 MHz. As apparent from FIG. 4, it can be understood that the SNDR is limited by a distortion due to the clock skew when the clock skew is large.
One method for avoiding the clock skew is to use the sample hold amplifier disclosed in the Non-Patent Document 8. Since the sample hold circuit in each channel samples the output signal from the sample hold amplifier, no clock skew occurs and no RC mismatch occurs. However, the sample hold amplifier must operate at the maximum rate thereof, and this leads to the problem of difficulties in its being applied to a high-speed and high-resolution A/D converter.
Moreover, there is also a method for passively sampling the clock skew (See, for example, the Non-Patent Document 2). However, the method has the defects that a sampling switch of a series connection is added and a tracking time is short. The timing error can be suppressed to the minimum without changing the architecture of the time-interleaved A/D converter but by calibration. The calibration in this case actually includes error detection and calibration. A calibration method on the background is now under researches due to the fact that the sampling of the clock skew is difficult during device operation.
Further, the clock skew can be measured by using a calibration signal (See, for example, the Non-Patent Document 3 and the Patent Document 4) or a so-called blind estimation method (See, for example, the Non-Patent Documents 4 and 5). If the amount of clock skew is measured, calibration can be executed by an analog method for adjusting the sampling clock phase or a digital processing method for restructuring a correct sample by using a filter bank after time-interleaved A/D conversion. Regarding the calibration of RC mismatch, sufficient researches have not been performed yet. Further, the Non-Patent Document 6 describes that RC mismatch can also be calibrated simultaneously with the clock skew by adjusting the sampling clock phase.
FIG. 5 is a circuit diagram showing a structure of a sample hold circuit 1 for use in the time-interleaved A/D converter disclosed in the Non-Patent Document 3. Referring to FIG. 5, the sample hold circuit 1 is constituted by including a differential sample hold amplifier 10 that employs a switched capacitor. In this case, Cs is a sampling capacitor, switches 21 to 26 are turned on/off by a timing signal φ1, and switches 27 to 30 are turned on/off by the inverted signal φ1 of the timing signal φ1. Moreover, T1 and T2 are signal input terminals, T3 and T4 are signal output terminals, and T5 and T6 are reference voltage input terminals. The sample hold circuit 1 of FIG. 5 uses a method for performing digital correction of timing errors in the time-interleaved A/D converter, and the method superimposes a common mode signal on the input signal by replacing the signal into a calibration signal as shown in FIG. 5. The method is impractical because the load connected to the voltage source of the reference voltage is generally large and has had the problem of reference voltage fluctuations during the time-interleaved A/D conversion.
Moreover, the prior art blind estimation method, which needs no calibration signal, has its algorithm generally complicated and a problem that a large amount of data is necessary for convergence.